View UPD75328_8835455.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document no. ic-2763b (o. d. no. ic-7628d) date published november 1993 p printed in japan ? nec corporation 1990 data sheet mos integrated circuit m pd75328 4-bit single-chip microcomputer the mark h shows the major revised points. description the m pd75328 is one of the 75x series 4-bit single-chip microcomputer, and has a data processing capability comparable to that of an 8-bit microcomputer. in addition to high-speed operation with 0.95 m s minimum instruction execution time for the cpu, the m pd75328 can also process data in 1-, 4-, and 8-bit units. therefore, as a 4-bit single-chip microcomputer chip having a built-in lcd controller/driver and a/d converter, its data processing capability is the highest in its class in the world. the m pd75p328 with one-time prom, which is replaced with the internal mask rom for a m pd75328, is applicable for evaluating systems under development, or for small-scale production of developed systems. "detailed functions are described in the following user's manual. be sure to read it for designing." " m pd75328 user's manual: iem-5045" features capable of high-speed operation and variable instruction execution time to power save ? 0.95 m s, 1.91 m s, 15.3 m s (main system clock: operating at 4.19 mhz) ? 122 m s (subsystem clock: operating at 32.768 khz) 75x architecture comparable to that for an 8-bit microcomputer is employed built-in programmable lcd controller/driver built-in 8-bit resolution a/d converter: 6 channels clock operation at reduced power dissipation: 5 m a typ. (operating at 3 v) timer function: 3 channels interrupt functions especially enhanced for applications, such as remote control receiver pull-up resistors can be provided for 35 i/o lines built-in nec standard serial bus interface (sbi) applications cameras, blood pressure gauges, airconditioners, etc. the information in this document is subject to change without notice. ordering information part number package quality grade m pd75328gc-xxx-3b9 80-pin plastic qfp ( n n 14mm) standard remarks : xxx is rom code number. please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
2 m pd75328 including the pins which also serve as lcd drive pins. excluding the pins which is specifically pro- vided for driving lcd. functional outline (1/2) item function number of basic 41 instructions instruction 0.95, 1.91, and 15.3 m s, (main system clock: operating at 4.19 mhz) execution time 122 m s (subsystem clock: operating at 32.768 khz) rom 8064 8-bit ram 512 4-bit general-purpose 4-bit manipulation: 8 4 banks, 8-bit manipulation: 4 4 banks registers i/o line 8 cmos input pins internal pull-up resistor specification by software 44 20 cmos input/output pins is possible (except p00). 8 cmos output pins also serve as segment pins 8 n-ch open-drain withstand voltage: 10v input/output internal pull-up resistor specification by mask option is possible. lcd controller/ ? lcd drive output pins driver ? segment output pins: 20 (cmos output pins: 8) ? common output pins: 4 ? capable of driving up to 20 4 segments ? display output mode: static, 1/2, 1/3, 1/4 duty a/d converter 8-bit resolution x 6 channels (successive approximation type) ? operating voltage v dd = 3.5 to 6.0 v ? a/d conversion speed 40.1 m s (operating at 4.19 mhz) 8-bit timer/event counter ? clock source: 4 steps ? event count is possible 8-bit basic interval timer timer 3 chs ? reference time generation (1.95, 7.82, 31.3, 250 ms: operating at 4.19 mhz) ? can be used as watchdog timer clock timer ? 0.5 second interval generation ? count clock source slectable (4.19 mhz/32.768 khz) ? clock advance mode (3.9 ms time interval generation) ? buzzer output (2 khz) clock synchronized serial interface serial ? internal nec standard serial bus interface (sbi mode) interface ? 3-line serial i/o mode ... msb/lsb first selectable ? 2-line serial i/o mode bit sequential special bit manipulation memory: 16 bits buffer clock output f, 524, 262, 65.5 khz (main system clock: 4.19 mhz) (pcl) buzzer output 2 khz (with main system clock or subsystem clock operated) (buz) vector interrupt ? external: 3 ? internal: 3 test input ? external: 1 ? internal: 1 internal memory
3 m pd75328 functional outline (2/2) item function system clock ? main system clock generation ceramic/crystal oscillator; 4.194304 mhz generator ? subsystem clock generation crysal oscillator: 32.768 khz standby stop/halt mode operating C40 to +85 c temperature range operating supply v dd = 2.7 to 6.0 v voltage package 80-pin plastic qfp ( n n 14 mm)
4 m pd75328 contents 1. pin configuration (top view) ........................................................................................ 6 2. block diagram ......................................................................................................................7 3. pin functions ........................................................................................................................8 3.1 port pins ........................................................................................................................................ 8 3.2 non port pins ............................................................................................................................ 10 3.3 pin input/output circuits ................................................................................................... 12 3.4 recommended processing of unused pins .................................................................. 14 3.5 selection of mask option ................................................................................................... 15 3.6 notes on using the p00/int4, and reset pins .............................................................. 15 4. memory configuration ................................................................................................. 16 5. peripheral hardware functions ............................................................................... 18 5.1 ports ............................................................................................................................................. 18 5.2 clock generator circuit ..................................................................................................... 19 5.3 clock output circuit ............................................................................................................. 20 5.4 basic interval timer .............................................................................................................. 21 5.5 watch timer ............................................................................................................................... 22 5.6 timer/event counter ............................................................................................................. 22 5.7 serial interface ....................................................................................................................... 24 5.8 lcd controller/driver ......................................................................................................... 26 5.9 a/d converter .......................................................................................................................... 28 5.10 bit sequential buffer .... 16 bits ....................................................................................... 29 6. interrupt functions ......................................................................................................... 29 7. standby functions ............................................................................................................ 31 8. reset function .................................................................................................................... 32 9. instruction set ................................................................................................................. 34 10. electrical specifications ............................................................................................. 40 11. characteristic curves (reference value) ............................................................ 53 12. package drawings ........................................................................................................... 59 13. recommended soldering conditions ...................................................................... 61
5 m pd75328 appendix a. comparison of features between pd75328 and pd75308 ........ 62 appendix b. development tools ...................................................................................... 63 appendix c. related documents ..................................................................................... 64 mm
6 m pd75328 p00-p03 : port 0 av ss : analog ground p10-p13 : port 1 an0-an5 : analog input 0-5 p20-p23 : port 2 s12-s31 : segment output 12-31 p30-p33 : port 3 com0-com3 : command output 0-3 p40-p43 : port 4 v lc0 -v lc2 : lcd power supply 0-2 p50-p53 : port 5 bias : lcd power supply bias control p60-p63 : port 6 lcdcl : lcd clock p70-p73 : port 7 sync : lcd synchronization p80-p83 : port 8 ti0 : timer input 0 bp0-bp7 : bit port pto0 : programmable timer output 0 kr0-kr7 : key return buz : buzzer clock sck : serial clock pcl : programmable clock si : serial input int0,int1,int4 : external vectored interrupt 0,1,4 so : serial output int2 : external test input 2 sb0,sb1 : serial bus 0,1 x1,x2 : main system clock oscillation 1,2 reset : reset input xt1,xt2 : subsystem clock oscillation 1,2 av ref : analog reference nc : no connection 1. pin configuration (top view) s31/bp7 com0 an2 p73/kr7 pd75328gc? ?b9 m p72/kr6 p71/kr5 p70/kr4 p63/kr3 p62/kr2 p61/kr1 p60/kr0 reset x2 x1 nc xt2 xt1 v dd av ref av ss an5 an4 an3 com1 com2 com3 bias vlc0 vlc1 vlc2 p40 p41 p42 p43 ss v p50 p51 p52 p53 p00/int4 p01/sck p02/so/sb0 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 s30/bp6 s29/bp5 s28/bp4 s27/bp3 s26/bp2 s25/bp1 s24/bp0 s23 s22 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 an1 an0 p83 p82 p81 p80 p33 p32 p31/sync p30/lcdcl p23/buz p22/pcl p21 p20/pto0 p13/ti0 p12/int2 p11/int1 p10/int0 p03/si/sb1
7 m pd75328 2. block diagram an0?n5 6 av ref av ss ti0/p13 a/d converter basic interval timer intbt timer/event counter #0 intt0 pto0/p20 buz/p23 watch timer intw f lcd intcsi clocked serial interface si/sb1/p03 so/sb0/p02 sck/p01 program counter (13) alu cy sp (8) bank int0/p10 int1/p11 int2/p12 int4/p00 kr0/p60 ?r7/p73 8 interrupt control bit seq. buffer (16) program memory (rom) 8064 8 bits decode and control general reg. data memory (ram) 512 4 bits f /2 x n v dd v ss reset pcl/p22 xt1 xt2 x1 x2 sub main clock output control clock divider system clock generator stand by control cpu clock f lcd sync/p31 lcdcl/p30 bias v -v lc0 lc2 3 lcd controller /driver 4 8 12 com0-com3 s24/bp0 -s31/bp7 s12-s23 port 8 p80-p83 4 port 7 p70-p73 4 port 6 p60-p63 4 port 5 p50-p53 4 port 4 p40-p43 4 port 3 p30-p33 4 port 2 p20-p23 4 port 1 p10-p13 4 port 0 p00-p03 4
8 m pd75328 3. pin functions 3.1 port pins (1/2) input/ output circuit type* 1 p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30* 2 p31* 2 p32* 2 p33* 2 p40-43* 2 p50-53* 2 pin name input/output function 8-bit i/o when reset also served as int4 sck so/sb0 so/sb1 int0 int1 int2 ti0 pto0 pcl buz lcdcl sync 4-bit input port (port0) pull-up resistors can be specified in 3-bit units for the p01 to p03 pins by software. with noise elimination function 4-bit input port (port1) internal pull-up resistors can be specified in 4-bit units by software. 4-bit input/output port (port2) internal pull-up resistors can be specified in 4-bit units by software. programmable 4-bit input/output port (port3) this port can be specified for input/ output in bit units. internal pull-up resistors can be specified in 4-bit units by software. n-ch open-drain 4-bit input/output port (port4) internal pull-up resistors can be specified in bit units. (mask option) resistive voltage is 10 v in the open- drain mode. n-ch open-drain 4-bit input/output port (port5) internal pull-up resistors can be specified in bit units. (mask option) resistive voltage is 10 v in the open- drain mode. input input input input high level (with internal pull-up resistor) or high imped- ance b b -c e-b e-b m m x x x x *1: circles indicate schmitt trigger inputs. 2: can directly drive led. input input/ output input/ output input/ output input input/ output input/ output input/ output input/ output l l f -a m -c f -b high level (with internal pull-up resistor) or high imped- ance
m pd75328 p60 p61 p62 p63 p70 p71 p72 p73 p80 p81 p82 p83 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 s24 s25 s26 s27 s28 s29 s30 s31 l l input/ output input/ output input/ output output output also served as programmable 4-bit input/output port (port6) this port can be specified for input/ output in bit units. internal pull-up resistors can be specified in 4-bit units by software. input f -a 4-bit input/output port (port7) internal pull-up resistors can be specified in 4-bit units by software. input f -a pin name input/output function 8-bit i/o when reset 4-bit input/output port (port8) internal pull-up resistors can be specified in 4-bit units by software. x input e-b 1-bit output port (bit port) shared with a segment output pin. x *2 g-c *1: circles indicate schmidt trigger inputs. 2: for bp0-7, v lc1 indicated below are selected as the input source. however, the output level is changed depending on bp0-7 and the v lc1 external circuits. example: since bp0-7 are connected to each other within the m pd75328 as shown in the diagram below, the output level of bp0-7 depends on the sizes of r 1 , r 2 and r 3 . pd75328 m on on bp bp v dd r 2 r 3 v lc1 r 1 1 0 9 3.1 port pins (2/2) input/ output circuit type* 1
10 m pd75328 parallel falling edge detection testable input/output parallel falling edge detection testable input/output segment signal output segment signal output common signal output lcd drive power step-down resistor network (mask option) external expanded driver for disconnect output externally expanded driver for clock output externally expanded driver sync clock output 6-bit analog input for a/d converter a/d converter reference voltage input gnd potential for a/d converter reference voltage input. connected to v ss . ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0-kr3 kr4-kr7 s12-s23 s24-s31 com0- com3 v lc0 -v lc2 bias lcdcl* 3 sync* 3 an0-an5 av ref av ss input output input/ output input/ output input/ output input/ output input/ output input input input input/ output input/ output output output output output input/ output input/ output input input p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60-p63 p70-p73 bp0-7 p30 p31 input input input input input input input input input input input input *4 *4 *4 *5 input input input input b -c e-b e-b e-b f -a f -b m -c b b -c b -c f -a f -a g-a g-c g-b e-b e-b y z pin name input/output also served as functon when reset input/ output circuit type* 1 3.2 non port pins timer/event counter external event pulse input timer/event counter output clock output fixed frequency output (for buzzer or for trim- ming the system clock) serial clock input/output serial data output serial bus input/output serial data input serial bus input/output edge detection vector interrupt input (both rising and falling edge detection are effective) edge detection vector interrupt input (detection edge can be selected) edge detection testable input (rising edge detection) clock synchronous asynchronous asynchronous
m pd75328 also served as to connect the crystal/ceramic oscillator to the main system clock generator. when inputting the external clock, input the external clock to pin x1, and the reverse phase of the external clock to pin x2. to connect the crystal oscillator to the subsystem clock generator. when the external clock is used, pin xt1 inputs the external clock. in this case, pin xt2 must be left open. pin xt1 can be used as a 1-bit input pin. system reset input no connection positive power supply gnd x1, x2 xt1, xt2 input reset nc * 2 v dd v ss b *1: circles indicate schmidt trigger inputs. 2: when sharing the printed circut board with the m pd75p328, the nc pin must be connected to v dd . 3: these pins are provided for future system expansion. at present, these pins are used only as pins p30 and p31. 4: for these display output, v lcx indicated below are selected as the input source. s12 to s31: v lc1 , com0 to com2: v lc2 , com3: v lc0 however, display output level varies depending on the particular display output and v lcx external circuit. example: since bp0-7 are connected to each other within the m pd75328 as shown in the diagram below, the output level of bp0-7 depends on the size of r 1 , r 2 and r 3 . 5: step-down resistor network provided : low level step-down resistor network not provided : high impedance pd75328 m on on bp bp v dd r 2 r 3 v lc1 r 1 1 0 11 pin name input/output function when reset (cont'd) input/ output circuit type* 1
12 m pd75328 3.3 pin input/output circuits the following shows a simplified input/output circuit diagram for each pin of the m pd75328. type a (for type e?) type d (for type e b, f type b type e? in v dd p?h n?h input buffer of cmos standard data output disable out p?h n?h push?ull output that can be set in a output high?mpedance state (both p?h and n?h are off) in schmitt trigger input with hysteresis characteristics data output disable type d type a p.u.r. enable v dd p.u.r. p?h in/out p.u.r. : pull?p resistor p.u.r. enable v dd p.u.r. p?h type b? type f? in data output disable type d type b p.u.r. enable v dd p.u.r. p?h in/out p.u.r. : pull?p resistor p.u.r. : pull ?p resistor schmitt trigger input with hysteresis characteristics a) v dd
13 m pd75328 p-ch type m? data output disable p.u.r. enable v dd p.u.r. in/out p?h n-ch type f? type m data output disable p.u.r. enable v dd in/out middle voltage input buffer (resistive voltage: +10 v) p.u.r. : pull?p resistor data output disable p.u.r. enable v dd p.u.r. p?h n-ch p-ch output disable (p) output disable (n) v dd (mask option) p.u.r. : pull?p resistor in/out type g c type g? p.u.r. : pull?p resistor type g? v dd v lc0 v lc0 v lc1 v lc2 seg data/bit port data p-ch n-ch out n-ch v lc1 v lc2 p-ch p-ch n-ch out n-ch v lc0 v lc1 v lc2 p-ch n-ch seg data com data out p-ch n-ch n-ch p-ch n-ch
14 m pd75328 pin recommended connections p00/int4 connect to v ss p01/sck p02/so/sb0 connect to v ss or v dd p03/si/sb1 p10/int0-p12/int2 p13/ti0 p20/pto0 p21 p22/pcl p23/buz p30-p33 input : connect to v ss or v dd p40-p43 output: open p50-p53 p60-p63 p70-p73 p80-p83 s12-s23 s24/bp0-s31/bp7 open com0-com3 v lc0 -v lc2 connect to v ss bias connect to v ss only when all of the v lc0 -v lc2 pins are unused, otherwise, open. xt1 connect to v ss or v dd xt2 open av ref connect to v ss av ss connect to v ss an0-an5 connect to v ss or v dd 3.4 recommended processing of unused pins connect to v ss type y n?h in p?h av ss v dd v dd av ss sampling c + input enable reference voltage (from a voltage tap of series resistor string) type z in av ss reference voltage
15 m pd75328 3.5 selection of mask option the following mask operations are available and can be specified for each pin. table 3-1 mask option selection pin mask option remarks p40-p43, p50-p53 with voltage dividing without voltage dividing specification in 4-bit resistor for lcd drive resistor for lcd drive units power source power source with feed back resistor without feed back resistor xt1, xt2 (when using the subsystem (when using the subsystem clock) clock) with pull-up resistor without pull-up resistor specification in bit units 3.6 notes on using the p00/int4, and reset pins in addition to the functions described in sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the m pd75328 are tested, is provided to the p00/int4 and reset pins. if a voltage exceeding v dd is applied to either of these pins, the m pd75328 is put into test mode. therefore, even when the m pd75328 is in normal operation, if noise exceeding the v dd is input into any of these pins, the m pd75328 will enter the test mode, and this will cause problems for normal operation. as an example, if the wiring to the p00/int4 pin or the reset pin is long, stray noise may be picked up and the above montioned problem may occur. therefore, all wiring to these pins must be made short enough to not pick up stray noise. if noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. connect a diode having a low v f across p00/int4 and reset, and v dd . connect a capacitor across p00/int4 and reset, and v dd . v lc0 -v lc2 bias v dd v dd p00/int4, reset v dd v dd p00/int4, reset low v f diode h
16 m pd75328 fig. 4-1 program memory map 4. memory configuration program memory (rom) ... 8064 words 8 bits ? 0000h, 0001h : vector table to which address from which program is started is written after reset ? 0002h-000bh : vector table to which address from which program is started is written after interrupt ? 0020h-007fh : table area referenced by geti instruction data memory ? data area .... 512 words 4 bits (000hC1ffh) ? peripheral hardware area .... 128 words 4 bits (f80hCfffh) 765 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 mbe 0 0 internal reset start address (upper 5 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 5 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 5 bits) int0 start address (lower 8 bits) int1 start address (upper 5 bits) int1 start address (lower 8 bits) intcsi start address (upper 5 bits) intcsi start address (lower 8 bits) intt0 start address (upper 5 bits) intt0 start address (lower 8 bits) 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1f7fh geti instruction reference table 0 brcb ! caddr instruction branch address callf !faddr instruction entry address br ! addr instruction branch address call ! addr instruction subroutine entry address br $addr instruction relational branch address (?5 to ?, +2 to +16) branch destination address and subroutine entry address for geti instruction address
17 m pd75328 data area static ram (512 x 4) stack area (8 x 4) 000h 007h 256 x 4 (248 x 4) 0ffh 100h 1ebh bank 0 256 x 4 (236 x 4) not provided 128 x 4 f80h fffh peripheral hardware area bank 15 bank 1 (20 x 4) 1ech 1ffh general-purpose register area display data memory 008h fig. 4-2 data memory map
18 m pd75328 5. peripheral hardware functions 5.1 ports i/o ports are classified into the following 4 kinds: cmos input (port0, 1) : 8 cmos input/output (port2, 3, 6, 7, and 8) : 20 cmos output (bp0-bp7) : 8 n-ch open-drain input/output (port4, 5) : 8 total : 44 table 5-1 port function remarks multiplexed with int4, sck, so/sb0, and si/sb1 multiplexed with int0- int2 and ti0 multiplexed with pto0, pcl, and buz multiplexed with kr4-kr7 multiplexed with lcdcl and sync multiplexed with kr0-kr3 can be connected to a pull-up resistor in 1-bit units by using mask option. port name port0 port1 port2 port7 port8 port3 port6 port4 * port5 * bp0-bp7 function 4-bit input 4-bit input/output 4-bit input/output (n-ch open-drain, 10 v) 1-bit output operation and feature can be always read or tested regardless of operation mode of multiplexed pin. can be set in input or output mode in 4-bit units. ports 6 and 7 are used in pairs to input/output data in 8-bit units. can be set in input or output mode in 1-bit units. can be set in input or output mode in 4-bit units. ports 4 and 5 are used in pairs to input/output data in 8-bit units. output data in 1-bit units. can be used as lcd drive segment output pins s24-s31 through software. *: can directly drive led.
19 m pd75328 5.2 clock generator circuit the operation of the clock generator circuit is determined by the processor clock control regiser (ppc) and system clock control register (scc). this circuit can generate two types of clocks: main system clock and subsystem clock. in addition, it can also change the instruction execution time. 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz) 122 m s (subsystem clock: 32.768 khz) *: instruction execution. remarks 1: f x = main system clock frequency 2: f xt = subsystem clock frequency 3: f= cpu clock 4: pcc: processor clock control register 5: scc: system clock control register 6: one clock cysle (t cy ) of f is one machine cycle of an instruction. for t cy , refer to ac characteristics in 10. electrical specifications. fig. 5-1 clock generator block diagram v dd v dd xt1 xt2 x1 x2 f xt f x lcd controller /driver watch timer subsystem clock oscillator main system clock oscillator 1/2 1/16 1/8 to 1/4096 frequency divider ?basic interval timer (bt) ?timer/event counter ?serial interface ?watch timer ?lcd controller/driver ?a/d converter ?int0 noise rejecter circuit ?clock output circuit internal bus wm.3 scc scc3 scc0 pcc pcc0 pcc1 pcc2 pcc3 halt* stop* 4 pcc2, pcc3 clear signal stop f/f qs r q s r halt f/f oscillator disable signal frequency divider 1/4 selector selector f ?cpu ?int0 noise rejecter circuit ?clock output circuit wait release signal from bt reset signal standby release signal from interrupt control circuit h
20 m pd75328 5.3 clock output circuit the clock output circuit outputs clock pulse from the p22/pcl pin. this clock pulse is used for the remote control output, peripheral lsis, etc. fig. 5-2 clock output circuit configuration remarks: a measures to prevent outputting narrow width pulse when selecting clock output enable/disable is taken. selector output buffer pcl/p22 bit 2 of pmgb port2.2 port 2 input/ output mode specification bit p22 output latch internal bus clom3 0 clom1 clom0 clom 4 f f x /2 3 f x /2 4 f x /2 6 from the clock generator
21 m pd75328 5.4 basic interval timer the m pd75328 is provided with the 8-bit basic interval timer. the basic interval timer has these functions: interval timer operation which generates a reference time interrupt watchdog timer application which detects a program runaway selects the wait time for releasing the standby mode and counts the wait time reads out the count value from the clock generator f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx clear basic interval timer (8-bit frequency divider circuit) 3 4 8 bt clear set signal bt interrupt request flag irqbt wait release signal for standby release vector interrupt request signal internal bus btm3 btm2 btm1 btm0 btm set1* remarks : *: instruction execution fig. 5-3 basic interval timer configuration
22 m pd75328 5.5 watch timer the m pd75328 has a built-in 1-ch watch timer. the watch timer is configured as shown in fig. 5-4. sets the test flag (irqw) with 0.5 sec interval. the standby mode can be released by irqw. 0.5 second interval can be generated either from the main system clock or subsystem clock. time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. this is convenient for program debugging, test, etc. fixed frequency (2.048 khz) can be output to the p23/buz pin. this can be used for beep and system clock frequency trimming. the frequency divider circuit can be cleared so that zero second watch start is possible. ( ) is for f x = 4.194304 mhz, f xt = 32.768 khz. fig. 5-4 watch timer block diagram 5.6 timer/event counter the m pd75328 has a built-in 1-ch timer/event counter. the timer/even counter has these functions: programmable interval timer operation outputs square-wave signal of an arbitrary frequency to the pto0 pin. event counter operation divides the ti0 pin input in n and outputs to the pto0 pin (frequency divider operation). supplies serial shift clock to the serial interface circuit. count condition read out function wm7 0 0 0 wm3 wm2 wm1 wm0 selector frequency divider f w 2 6 (512 hz: 1.95 ms) f w 2 7 (256 hz: 3.91 ms) f lcd intw (irqw set signal) f w 2 14 (2 hz 0.5 sec) selector f w (32.768 khz) f w 16 (2.048 khz) clear f x 128 (32.768 khz) f xt (32.768 khz) from the clock generator wm port2.3 bit 2 of pmgb output buffer p23/buz p23 output latch port 2 input/output mode bit test instruction 8 internal bus
23 m pd75328 internal bus 8 8 set1* tm07 tm06 tm05 tm04 tm03 tm02 tm01 tm00 tm0 port1.3 input buffer p13/ti0 from the clock generator mpx *: instruction execution timer operation start signal cp 8 8 modulo register (8) comparator (8) count register (8) clear t0 tmod0 reset toe0 port2.0 bit 2 of pgmb to serial interface p20/pto0 intt0 irqt0 set signal () reset irqt0 clear signal output buffer tout f/f to enable flag p20 output latch port 2 input/ output mode coinci- dence 8 fig. 5-5 timer/event counter block diagram
24 m pd75328 5.7 serial interface the m pd75328 is equipped with an 8-bit clocked serial interface that operates in the following four modes: operation stop mode three-line serial i/o mode two-line serial i/o mode sbi mode (serial bus interface mode)
25 m pd75328 internal bus 8/4 8 88 csim p03/si/sb1 p02/so/sb0 p01/sck p01 output latch selector selector bit test slave address register (sva) address comparator shift register (sio) set clr bit manipulation (8) (8) coincidence signal sbic relt cmdt so latch bit test ackt acke bsye busy/ acknowledge output circuit bus release/ command/ acknowledge detector circuit reld cmdd ackd serial clock counter serial clock control circuit intcsi control circuit serial clock selector i ntcsi irqcsi set signal ( ) dq f x /2 3 f x /2 4 f x /2 6 tout f/f (from timer/ event counter) external sck (8) fig. 5-6 serial interface block diagram
26 m pd75328 5.8 lcd controller/driver the m pd75328 is provided with a display controller that generates segment and common signals and a segment driver and a common driver that can directly drive an lcd panel. these lcd controller and drivers have the following functions: generate segment and common signals by automatically reading the display data memory by means of dma five display modes selectable ? static ? 1/2 duty (divided by 2), 1/2 bias ? 1/3 duty (divided by 3), 1/2 bias ? 1/3 duty (divided by 3), 1/3 bias ? 1/4 duty (divided by 4), 1/3 bias four types of frame frequencies selectable in each display mode up to 20 segment signals (s12-s31) and four common signals (com0-com3) can be output. four segment signal output pins (s24-s27, s28-s31) can be used as an output port (bp0-bp3, bp4- bp7). dividing resistor for lcd driving power source can be provided (by mask option). ? all bias modes and lcd drive voltages can be used. ? current flowing to dividing resistor can be cut when display is off. display data memory not used for display can be used as ordinary data memory. can also operate on subsystem clock.
27 m pd75328 internal bus 1ffh 3210 display data memory 3210 1feh 3210 3210 1f9h 3210 3210 1f8h 3210 3210 1ech 3210 3210 multi- plexer selector s31/bp7 common driver s30/bp6 s24/bp0 s23 s12 com3 com2 com1 com0 v p31/ sync lc2 v lc1 v lc0 lcd driving voltage control p30/ lcdcl timing controller f lcd display mode register display control register port 3 out- put latch 10 port mode re- gister group a 10 48448 fig. 5-7 lcd controller/driver block diagram segment driver
28 m pd75328 5.9 a/d converter the m pd75328 is provided with an 8-bit resolution analog-to-digital (a/d) converter with six channels of analog inputs (an0-an5). this a/d converter is of a successive approximation type. an0 an1 an2 an3 an4 an5 av ref av ss multiplexer sample hold circuit + tap decoder r/2 r/2 rr r serial resistor string 8 8 sa register (8) control circuit internal bus 0 adm6 adm5 adm4 soc eoc adm1 0 adm comparator 8 fig. 5-8 block diagram of a/d converter
29 m pd75328 5.10 bit sequential buffer .... 16 bits the bit sequential buffer is a data memory specifically provided for bit manipulation. with this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. therefore, this buffer is very useful for processing long data in bit units. remarks: for the pmem.@l addressing, the specification bit is shifted according to the l register. fig. 5-9 bit sequential buffer format 6. interrupt functions the m pd75328 has 6 different interrupt sources and multiplexed interrupt with priority order. in addition to that, the m pd75328 is also provided with two types of test sources, of which int2 has two types of edge detection testable inputs. the interrupt control circuit of the m pd75328 has these functions: hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (iexxx) and interrupt master enable flag (ime). the interrupt start address can be arbitrarily set. interrupt request flag (irqxxx) test function (an interrupt generation can be confirmed by means of software). standby mode release (interrupts to be released can be selected by the interrupt enable flag). address bit symbol l register 32103210 32103210 l = f l = c l = b l = 8 l = 7 l = 4 l = 3 l = 0 bsb3 bsb2 bsb1 bsb0 decs l incs l fc3h fc2h fc1h fc0h
30 m pd75328 internal bus 213 im2 im1 im0 irqbt int4 /p00 int0 /p10 int1 /p11 int2 /p12 kr0/p60 kr7/p73 noise elimination circuit int bt intcsi intt0 intw selector both edge detection circuit edge detection circuit edge detection circuit rising edge detection circuit falling edge detection circuit irq4 irq0 irq1 irqcsi irqt0 irqw irq2 im2 interrupt enable flag (ie ) ime vrqn decoder ist0 priority control circuit vector table address generator standby release signal fig. 6-1 interrupt control block diagram
31 m pd75328 7. standby functions the m pd75328 has two different standby modes (stop mode and halt mode) to reduce the power consumption while waiting for program execution. table 7-1 each status in standby mode setting instruction stop instrtuction halt instruction can be set only when operating on the main system clock can be set either with the main system clock or the subsystem clock operation status clock generator only the main system clock stops its operation. only the cpu clock f stops its operation. (oscillation continues) basic interval timer no operation can operate only when main system clock oscillates (sets irqbt at reference time interval) serial interface can operate only when the external sck input is selected for the serial clock can operate only when main system clock oscillates, or when external sck input is selected as serial clock timer/event counter can operate only when the ti0 pin input is selected for the count clock can operate only when main system clock oscillates, or when ti0 pin input is selected as count clock watch timer can operate when f xt is selected as the count clock can operate release signal an interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the reset signal input an interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the reset signal input item mode stop mode halt mode lcd controller can operate only when f xt is selected as lcdcl can operate a/d convertor no operation can operate only when the main system clock is operating. external interrupt int1, int2, and int4 can operate. only int0 can not operate. cpu no operation system clock for setting
32 m pd75328 8. reset function when the reset signal is input, the m pd75328 is reset and each hardware is initialized as indicated in table 8-1. fig. 8-1 shows the reset operation timing. reset input wait (31.3ms/4.19mhz) operation mode or standby mode halt mode operation mode internal reset operation fig. 8-1 reset operation by reset input table 8-1 status of each hardware after reset (1/2) hardware reset input in standby mode reset input during operation program counter (pc) the contents of the lower 5 bits of address 0000h of the program memory are set to pc12-8, and the contents of address 0001h are set to pc7-0. the contents of the lower 5 bits of address 0000h of the program memory are set to pc12-8, and the contents of address 0001h are set to pc7-0. psw carry flag (cy) retained undefined skip flag (sk0-2) 0 0 interrupt status flag (ist0) 0 0 bank enable flag (mbe) the contents of bit 7 of address 0000h of the program memory are set to mbe. the contents of bit 7 of address 0000h of the program memory are set to mbe. stack pointer (sp) undefined undefined data memory (ram) retained * 1 undefined general-purpose register (x, a, h, l, d, e, b, c) retained undefined bank selection register (mbs) 0 0 basic interval timer counter (bt) undefined undefined timer/event counter counter (t0) 0 0 module register (tmod0) ffh ffh mode register (tm0) 0 0 toe0, tout f/f 0, 0 0, 0 mode register (btm) 0 0 mode register (wm) 0 watch timer 0
33 m pd75328 serial shift register (sio) retained undefined interface operation mode 0 0 register (csim) sbi control register 0 0 (sbic) slave address register retained undefined (sva) clock processor clock control 0 0 generator, register (pcc) clock output system clock control 0 0 circuit register (scc) clock output mode 0 0 register (clom) lcd display mode register 0 0 controller (lcmd) display control 0 0 register (lcdc) a/d converter mode regiseter (adm), 04h (eoc = 1) 04h (eoc = 1) eoc sa register 7fh 7fh interrupt interrupt request flag reset (0) reset (0) function (irqxxx) interrupt enable flag 0 0 (iexxx) interrupt master enable 0 0 flag (ime) int0, int1, int2 mode 0, 0, 0 0, 0, 0 registers (im0, 1, 2) digital port output buffer off off output latch clear (0) clear (0) input/output mode 0 0 register (pmga, b, c) pull-up resistor 0 0 specification register (poga, b) pin states p00-p03, p10-p13, input input p20-p23, p30-p33, p60-p63, p70-p73, p80-p83 p40-p43, p50-p53 ? internal pull-up resistors same as at left ... high level ? open drain ... high impedance s12-s23, *2 *2 com0-com3 bias ? internal step-down resistors same as at left ... low level ? external step-down resistors ... high impedance bit sequential buffer (bsb0-3) retained specified hardware reset input during operation reset input in standby mode table 8-1 status of each hardware after reset (2/2)
34 m pd75328 *1 : data of address 0f8h to 0fdh of the data memory becomes undefined when a reset signal is input. 2: select v lcx as shown below as the input source for each display output. s12-31 : v lc1 com0-2 :v lc2 com3 : v lc0 however, the level of each display output varies according to the display output and the external circuit for v lcx . 9. instruction set (1) operand representation and description describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to ra75x assembler package user's manual - language (eeu-730)). with some instructions, only one operand should be selected from several operands. the uppercase characters, +, and C are keywords and must be described as is. describe an appropriate numeric value or label as immediate data. representation description reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rpa hl, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label bit 2-bit immediate data or label fmem fb0h to fbfh,ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr 0000h to 1f7fh immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (where bit0 = 0) or label portn port0 to port8 iexxx iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew mbn mb0, mb1, mb15
35 m pd75328 (2) legend of operation field a : a register; 4-bit accumulator b : b register; 4-bit accumulator c : c register; 4-bit accumulator d : d register; 4-bit accumulator e : e register; 4-bit accumulator h : h register; 4-bit accumulator l : l register; 4-bit accumulator x : x register; 4-bit accumulator xa : register pair (xa); 8-bit accumulator bc : register pair (bc); 8-bit accumulator de : register pair (de); 8-bit accumulator hl : register pair (hl); 8-bit accumulator pc : program counter sp : stack pointer cy : carry flag; or bit accumulator psw : program status word mbe : memory bank enable flag portn : port n (n = 0 to 8) ime : interrupt mask enable flag iexxx : interrupt enable flag mbs : memory bank selector register pcc : processor clock control register . : delimiter of address and bit (xx) : contents addressed by xx xxh : hexadecimal data
36 m pd75328 (3) symbols in addressing area field *1 mb = mbe . mbs (mbs = 0, 1, 15) *2 mb = 0 *3 mbe = 0 : mb = 0 (00h-7fh) data memory mb = 15 (80h-ffh) addressing mbe = 1 : mb = mbs (mbs = 0, 1, 15) *4 mb = 15, fmem = fb0h-fbfh, ff0h-fffh *5 mb = 15, pmem = fc0h-fffh *6 addr = 000h-1f7fh *7 addr = (current pc) C 15 to (current pc) C 1 (current pc) + 2 to (current pc) + 16 program *8 caddr = 0000h-0fffh (pc 12 = 0) or memory 1000h-1f7fh (pc 12 = 1) addressing *9 faddr = 0000h-07ffh *10 taddr = 0020h-007fh remarks 1: mb indicates memory bank that can be accessed. 2: in *2, mb = 0 regardless of mbe and mbs. 3: in *4 and *5, mb = 15 regardless of mbe and mbs. 4: *6 to *10 indicate areas that can be addressed. (4) machine cycle field in this field, s indicates the number of machine cycles required when an instruction having a skip function skips. the value of s varies as follows: when no instruction is skipped .................................................................................. s = 0 when 1-byte or 2-byte instruction is skipped ........................................................... s = 1 when 3-byte instruction (br ! addr or call ! addr) is skipped ............................ s = 2 note : the geti instruction is skipped in one machine cycle. one machine cycle equals to one cycle of the cpu clock f , (=t cy ), and can be changed in three steps depending on the setting of the processor clock control register (pcc).
37 m pd75328 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area transfer mov a, #n4 1 1 a n4 string effect a reg1, #n4 2 2 reg1 n4 xa, #n8 2 2 xa n8 string effect a hl, #n8 2 2 hl n8 string effect b rp2, #n8 2 2 rp2 n8 a, @hl 1 1 a (hl) *1 a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 @hl, a 1 1 (hl) a*1 @hl, xa 2 2 (hl) xa *1 a,mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 mem, a 2 2 (mem) a*3 mem, xa 2 2 (mem) xa *3 a, reg 2 2 a reg xa, rp 2 2 xa rp reg1, a 2 2 reg1 a rp1, xa 2 2 rp1 xa xch a, @hl 1 1 a (hl) *1 a, @rpa1 1 1 a (rpa1) *2 xa, @hl 2 2 xa (hl) *1 a, mem 2 2 a (mem) *3 xa, mem 2 2 xa (mem) *3 a, reg1 1 1 a reg1 xa, rp 2 2 xa rp movt xa, @pcde 1 3 xa (pc 12-8 +de) rom xa, @pcxa 1 3 xa (pc 12-8 +xa) rom arith- adds a, #n4 1 1+s a a+n4 carry metic a, @hl 1 1+s a a+(hl) *1 carry opera- addc a, @hl 1 1 a, cy a+(hl)+cy *1 tion subs a, @hl 1 1+s a a-(hl) *1 borrow subc a, @hl 1 1 a, cy a-(hl)-cy *1 and a, #n4 2 2 a a ? n4 a, @hl 1 1 a a ? (hl) *1 or a, #n4 2 2 a a M n4 a, @hl 1 1 a a M (hl) *1 xor a, #n4 2 2 a a M n4 a, @hl 1 1 a a M (hl) *1 accumu- rorc a 1 1 cy a 0 , a 3 cy, a n-1 a n lator manipu- not a 2 2 a a lation
38 m pd75328 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area incre- incs reg 1 1+s reg ? reg+1 reg = 0 ment/ @hl 2 2+s (hl) ? (hl)+1 *1 (hl) = 0 decre- mem 2 2+s (mem) ? (mem)+1 *3 (mem) = 0 ment decs reg 1 1+s reg ? reg-1 reg = fh compare ske reg, #n4 2 2+s skip if reg = n4 reg = n4 @hl, #n4 2 2+s skip if (hl) = n4 *1(hl) = n4 a, @hl 1 1+s skip if a = (hl) *1 a = (hl) a, reg 2 2+s skip if a = reg a = reg carry set1 cy 1 1 cy ? 1 flag clr1 cy 1 1 cy ? 0 manipu- skt cy 1 1+s skip if cy = 1 cy = 1 lation not1 cy 1 1 cy ? cy memory/ set1 mem.bit 2 2 (mem.bit) ? 1*3 bit fmem.bit 2 2 (fmem.bit) ? 1 *4 manipu- pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 1*5 lation @h+mem.bit 2 2 (h + mem 3-0 .bit) ? 1*1 clr1 mem.bit 2 2 (mem.bit) ? 0 *3 fmem.bit 2 2 (fmem.bit) ? 0 *4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 0*5 @h+mem.bit 2 2 (h+mem 3-0 .bit) ? 0*1 skt mem.bit 2 2+s skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+s skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7-2 +l 3-2 .bit (l 1-0 )) = 1 *5 (pmem.@l) = 1 @h+mem.bit 2 2+s skip if (h + mem 3-0 .bit) = 1 *1 (@h+mem.bit) = 1 skf mem.bit 2 2+s skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+s skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2+s skip if (pmem 7-2 +l 3-2 .bit (l 1-0 )) = 0 *5 (pmem.@l) = 0 @h+mem.bit 2 2+s skip if (h + mem 3-0 .bit) = 0 *1 (@h+mem.bit) = 0 sktclr fmem.bit 2 2+s skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2+s skip if (pmem 7-2 +l 3-2 .bit *5 (pmem.@l) = 1 (l 1-0 )) = 1 and clear @h+mem.bit 2 2+s skip if (h+mem3-0.bit) = 1 and clear *1 (@h+mem.bit) = 1 and1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit(l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 or1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit (l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1 xor1 cy,fmem.bit 2 2 cy ? cy (fmem.bit) *4 cy,pmem.@l 2 2 cy ? cy (pmem 7-2 +l 3-2 .bit (l 1-0 )) *5 cy,@h+mem.bit 2 2 cy ? cy (h+mem 3-0 .bit) *1
39 m pd75328 ma- ad- instruc- mne- operand bytes chine operation dress- skip tions monics cyc- ing conditions les area branch br addr pc 12-0 addr *6 (the most suitable instruction is selectable from among br !addr, brcb !caddr, and br $addr depending on the assembler.) !addr 3 3 pc 12-0 addr *6 $addr 1 2 pc 12-0 addr *7 brcb !caddr 2 2 pc 11-0 caddr 11-0 *8 subrou- call !addr 3 3 (sp-4)(sp-1)(sp-2) pc 11-0 *6 tine/ (sp-3) mbe, 0, 0, pc 12 stack pc 12-0 addr, sp sp-4 control callf !faddr 2 2 (sp-4)(sp-1)(sp-2) pc 11-0 *9 (sp-3) mbe, 0, 0, pc 12 pc 12-0 00, faddr, sp sp-4 ret 1 3 mbe, x, x, pc 12 (sp+1) pc 11-0 (sp)(sp+3)(sp+2) sp sp+4 rets 1 3+s mbe, x, x, pc 12 (sp+1) undefined pc 11-0 (sp)(sp+3)(sp+2) sp sp+4, then skip unconditionally ret1 1 3 mbe, x, x, pc 12 (sp+1) pc 11-0 (sp)(sp+3)(sp+2) psw (sp+4)(sp+5), sp sp+6 push rp 1 1 (sp-1)(sp-2) rp, sp sp-2 bs 2 2 (sp-1) mbs, (sp-2) 0, sp sp-2 pop rp 1 1 rp (sp+1)(sp), sp sp+2 bs 2 2 mbs (sp+1), sp sp+2 inter- ei 2 2 ime 1 rupt iexxx 2 2 iexxx 1 control di 2 2 ime 0 iexxx 2 2 iexxx 0 i/o in * 1 a,portn 2 2 a port n (n = 0-8) xa,portn 2 2 xa port n+1 ,port n (n = 4, 6) out * 1 portn,a 2 2 port n a (n = 2-8) portn,xa 2 2 port n+1 ,port n xa (n = 4, 6) cpu halt 2 2 set halt mode (pcc.2 1) control stop 2 2 set stop mode (pcc.3 1) nop 1 1 no operation special sel mbn 2 2 mbs n (n = 0, 1, 15) geti * 2 taddr 1 3 . where tbr instruction, *10 pc 12-0 (taddr) 4-0 +(taddr+1) . where tcall instruction, (sp-4)(sp-1)(sp-2) pc 11-0 (sp-3) mbe, 0, 0, pc 12 pc 12-0 (taddr) 4-0 +(taddr+1) sp sp-4 . except for tbr and tcall depends on instructions, referenced instruction execution of instruction (taddr)(taddr+1) *1: when executing the in/out instruction, mbe = 0, or mbe = 1, and mbs = 15. 2: the tbr, and tcall instructions are the assembler pseudo-instructions for the table definition of geti instruction. ......................................................... ............................. ......................................................... .............................
40 m pd75328 10. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd -0.3 to +7.0 v v i1 other than ports 4, 5 -0.3 to v dd +0.3 v input voltage v i2 ports 4, 5 w/pull-up -0.3 to v dd +0.3 v resistor open drain -0.3 to +11 v output voltage v o -0.3 to v dd +0.3 v high-level output i oh 1 pin -15 ma current all pins -30 ma low-level output i ol * 1 pin peak 30 ma current rms 15 ma other than ports 0, 2, 3, 5, 8 peak 100 ma rms 60 ma total of ports 4, 6, 7 peak 100 ma rms 60 ma operating temperature t opt -40 to +85 c storage temperature t stg -65 to +150 c *: rms = peak value x duty capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out pins other than thosemeasured are at 0 v 15 pf input/output c io 15 pf capacitance operating supply voltage parameter symbol conditions min. max. unit a/d converter supply voltage v dd 3.5 6.0 v ambient temperature t a -10 +70 c other circuits supply voltage v dd 2.7 6.0 v ambient temperatuare t a -40 +85 c
41 m pd75328 main system clock oscillator circuit characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) oscillator recommended item conditions min. typ. max. unit constants ceramic * 3 oscillation 1.0 5.0 * 4 mhz frequency(f xx )* 1 oscillation stabiliza- after v dd came to tion time* 2 min. of oscillation voltage range 4ms crystal * 3 oscillation 1.0 4.19 5.0 * 4 mhz frequency (f xx )* 1 oscillation stabiliza- v dd = 4.5 to 6.0 v 10 ms tion time* 2 30 ms external clock x1 input frequency 1.0 5.0 * 4 mhz (f x )* 1 x1 input high-, low-level widths (t xh , t xl ) 100 500 ns *1: the oscillation frequency and x1 input frequency are indicated only to express the characteristics of the oscillator circuit. for instruction execution time, refer to ac characteristics. 2: time required for oscillation to stabilize after v dd reaches the minimum value of the oscillation voltage range or the stop mode has been released. 3: the oscillators on the next page are recommended. 4: when the oscillation frequency is 4.19 mhz < fx 5.0 mhz, do not select pcc = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 m s, falling short of the rated minimum value of 0.95 m s. subsystem clock oscillator circuit characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) oscillator recommended item conditions min. typ. max. unit constants crystal oscillation 32 32.768 35 khz frequency (f xt ) oscillation stabiliza- v dd = 4.5 to 6.0 v 1.0 2 s tion time* 10 s external clock xt1 input frequency 32 100 khz (f xt )* xt1 input high-, low-level widths 5 15 m s (t xth , t xtl ) x1 x2 c1 c2 v dd x1 x2 c1 c2 v dd x1 x2 pd74hcu04 m h xt1 xt2 r c3 c4 v dd xt1 xt2 open
42 m pd75328 *: time required for oscillation to stabilize after v dd reaches the minimum value of the oscillation voltage range. note: when using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: ? keep the wiring length as short as possible. ? do not cross the wiring over the other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillator circuit at the same potential as v dd . do not connect the power source pattern through which a high current flows. ? do not extract signals from the oscillation circuit. the amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. when using the subsystem clock, therefore, exercise utmost care in wiring the circuit. recommended oscillation circuit constants main system clock: ceramic oscillator (t a = -40 to +85 c) csax.xxmg093 30 30 2.7 cstx.xxmg093 unnecessary unnecessary 2.7 csax.xxmgu 30 30 2.7 cstx.xxmgu unnecessary unnecessary 2.7 csax.xxmg 30 30 3.0 cstx.xxmg unnecessary unnecessary 3.0 kbr-2.0ms 2.00 47 47 2.7 kbr-4.0ms 4.00 33 33 2.7 kbr-5.0m 5.00 33 33 3.0 c1 (pf) murata mfg. co., ltd. frequency (mhz) product name manufac- turer kyoto ceramic co., ltd. max. (v) min. (v) recommended circuit constants operating voltage range 2.00 to 2.44 2.45 to 5.00 2.00 to 5.00 6.0 6.0 c2 (pf) p3 32.768 22 * 22 330 2.7 c3 (pf) kinseki frequency (mhz) product name manufac- turer max. (v) min. (v) recommended circuit constants operating voltage range 6.0 subsystem clock: crystal oscillator (t a = -10 to +60 c) c4 (pf) r (k w ) *: adjust the oscillation frequency in a range of c3 = 3 to 30 pf. hc-18u 2.0 to 5.0 22 * 22 2.7 hc-43u, 49/u c1 (pf) kinseki frequency (mhz) product name manufac- turer max. (v) min. (v) recommended circuit constants operating voltage range 6.0 c2 (pf) *: adjust the oscillation frequency in a range of c1 = 15 to 33 pf. main system clock: crystal oscillator (t a = -20 to +70 c)
43 m pd75328 dc characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit high-level input v ih1 ports 2, 3, 8 0.7v dd v dd v voltage v ih2 ports 0, 1, 6, 7, reset 0.8v dd v dd v v ih3 ports 4, 5 w/pull-up resistor 0.7v dd v dd v open-drain 0.7v dd 10 v v ih4 x1, x2, xt1 v dd -0.5 v dd v low-level input v il1 ports 2, 3, 4, 5, 8 0 0.3v dd v voltage v il2 ports 0, 1, 6, 7, reset 0 0.2v dd v v il3 x1, x2, xt1 0 0.4 v high-level output v oh1 v dd = 4.5 to 6.0 v v dd -1.0 v voltage i oh = -1 ma i oh = -100 m av dd -0.5 v v oh2 v dd = 4.5 to 6.0 v v dd -2.0 v i oh = -100 m a i oh = -50 m av dd -1.0 v low-level output v ol1 ports 3, 4, and 5 0.4 2.0 v voltage v dd = 4.5 to 6.0 v i ol = -15 ma v dd = 4.5 to 6.0 v 0.4 v i ol = 1.6 ma i ol = 400 m a 0.5 v sb0, 1 open-drain pull-up 0.2v dd v resistor 1 k w v ol2 v dd = 4.5 to 6.0 v 1.0 v i ol = 100 m a i ol = 50 m a 1.0 v high-level input i lih1 v in = v dd other than below 3 m a leakage current i lih2 x1, x2, xt1 20 m a i lih3 v in = 10 v ports 4, 5 20 m a (open-drain) low-level input i lil1 v in = 0 v other than below -3 m a leakage current i lil2 x1, x2, xt1 -20 m a high-level output i loh1 v out = v dd other than below 3 m a leakage current i loh2 v out = 10 v ports 4, 5 20 m a (open-drain) low-level output i lol v out = 0 v -3 m a leakage current internal pull-up resistor r l1 ports 0, 1, 2, 3, 6, 7, 8 v dd = 5.0 v 10% 15 40 80 k w (except p00) v in = 0v v dd = 3.0 v 10% 30 300 k w r l2 ports 4, 5 v dd = 5.0 v 10% 15 40 70 k w v out = v dd -2.0 v v dd = 3.0 v 10% 10 60 k w lcd drive voltage v lcd 2.5 v dd v lcd step-down resistor r lcd 60 100 140 k w lcd output voltage v odc i o = 5 m a0 0.2 v v deviation (common) * 1 lcd output voltage v ods i o = 1 m a0 0.2 v v deviation (segment) * 1 ports 0, 2, 3, 4, 5, 6, 7, and 8 bp0-7 (with two i oh outputs) ports 0, 2, 3, 6, 7, 8, and bias bp0-7 (with two i ol outputs) v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 2.7 v v lcd v dd
44 m pd75328 parameter symbol conditions min. typ. max. unit supply current * 2 i dd1 4.19 mhz* 3 crystal v dd = 5 v 10%* 4 2.5 8 ma oscillator v dd = 3 v 10%* 5 0.35 1.2 ma i dd2 c1 = c2 = 22pf halt mode v dd = 5 v 10% 500 1500 m a v dd = 3 v 10% 150 450 m a i dd3 32 khz* 6 crystal operation v dd = 3 v 10% 30 90 m a oscillator mode i dd4 halt mode v dd = 3 v 10% 5 15 m a i dd5 xt1 = 0 v v dd = 5 v 10% 0.5 20 m a stop mode v dd = 3 v 10% 0.1 10 m a t a = 25 c 0.1 5 m a *1: "voltage deviation" means the difference between the ideal segment or common output value (v lcdn : n = 0, 1, 2) and output voltage. 2: currents for the built-in pull-up resistor and the lcd step-down resistor are not included. 3: including when the subsystem clock is operated. 4: when operand in the high-speed mode with the processor clock control register (pcc) set to 0011. 5: when operated in the low-speed mode with the pcc set to 0000. 6: when operated with the subsystem clock by setting the system clock control register (scc) to 1011 to stop the main system clock operation.
45 m pd75328 a/d converter (t a = -10 to +85 c, v dd = 3.5 to 6.0 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit absolute accuracy* 1 2.5 v av ref v dd * 2 1.5 lsb conversion time t conv * 3 168/f x s sampling time t samp * 4 44/f x s analog input voltage v ian av ss av ref v analog input impedance r an 1000 m w av ref current i ref 0.25 2.0 ma *1: absolute accuracy excluding quantization error ( 1 C 2 lsb) 2: set adm1 as follows, in respect to the reference voltage of the ad converter (av ref ). adm1 can be set to either 0 or 1 when 0.6v dd av ref 0.65v dd 3: time since execution of conversion start instruction until eoc = 1 (f x = 4.19 mhz: 40.1 m s) 4: time since execution of conversion start instruction until end of sampling (f x = 4.19 mhz: 10.5 m s) 2.5 v 0.6 v dd 0.65 v dd v dd (3.5 to 6.0 v) adm1=0 adm1=1 av ref
46 m pd75328 ac characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time t cy w/main system clock v dd = 4.5 to 6.0 v 0.95 64 m s (minimum instruction 3.8 64 m s execution time w/sub-system clock 114 122 125 m s = 1 machine cycle)* 1 ti0 input frequency f ti v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz ti0 input high-, low- t tih ,v dd = 4.5 to 6.0 v 0.48 m s level widths t til 1.8 m s interrupt input high-, t inth , int0 *2 m s low-level widths t intl int1, 2, 4 10 m s kr0-7 10 m s reset low-level width t rsl 10 m s *1: the cpu clock ( f ) cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (scc), and processor clock control register (pcc). the figure on the right is cycle time t cy vs. supply voltage v dd characteristics at the main system clock. 2: 2t cy or 128/f x depending on the setting of the interrupt mode register (im0). 0123 456 0.5 1 2 3 4 5 6 30 supply voltage v dd [v] cycle time t cy [ s] t cy vs v dd (with main system clock) m 64 70
47 m pd75328 serial transfer operation two-line and three-line serial i/o modes (sck: internal clock output) parameter symbol conditions min. typ. max. unit sck cycle time t kcy1 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level t kl1 v dd = 4.5 to 6.0 v t kcy1 /2-50 ns widths t kh1 t kcy1 /2-150 ns si set-up time (vs. sck - ) t sik1 150 ns si hold time (vs. sck - )t ksi1 400 ns sck ? so output t kso1 r l = 1 k w ,v dd = 4.5 to 6.0 v 250 ns delay time c l = 100 pf* 1000 ns *: r l and c l are load resistance and load capacitance of the so output line. two-line and three-line serial i/o modes (sck: external clock input) parameter symbol conditions min. typ. max. unit sck cycle time t kcy2 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high-, low-level t kl2 v dd = 4.5 to 6.0 v 400 ns widths t kh2 1600 ns si set-up time (vs. sck - ) t sik2 100 ns si hold time (vs. sck - )t ksi2 400 ns sck ? so output t kso2 r l = 1 k w , c l = 100 pf* v dd = 4.5 to 6.0 v 300 ns delay time 1000 ns *: r l and c l are load resistance and load capacitance of the so output line.
48 m pd75328 sbi mode (sck: internal clock output (master)) parameter symbol conditions min. typ. max. unit sck cycle time t kcy3 v dd = 4.5 to 6.0 v 1600 ns 3800 ns sck high-, low-level t kl3 v dd = 4.5 to 6.0 v t kcy3 /2-50 ns widths t kh3 t kcy3 /2-150 ns sb0, 1 set-up time t sik3 150 ns (vs. sck ) sb0, 1 hold time t ksi3 t kcy3 /2 ns (vs. sck ) sck ? sb0, 1 output t kso3 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns delay time c l = 100 pf* 0 1000 ns sck ? sb0, 1 ? t ksb t kcy3 ns sb0,1 ?? sck t sbk t kcy3 ns sb0, 1 low-level width t sbl t kcy3 ns sb0, 1 high-level width t sbh t kcy3 ns *: r l and c l are load resistance and load capacitance of the so output line. sbi mode (sck: external clock input (slave)) parameter symbol conditions min. typ. max. unit sck cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high-, low-level t kl4 v dd = 4.5 to 6.0 v 400 ns widths t kh4 1600 ns sb0, 1 set-up time t sik4 100 ns (vs. sck ) sb0, 1 hold time t ksi4 t kcy4 /2 ns (vs. sck ) sck ? sb0, 1 output t kso4 r l = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns delay time c l = 100 pf* 0 1000 ns sck ? sb0, 1 ? t ksb t kcy4 ns sb0,1 ?? sck ? t sbk t kcy4 ns sb0, 1 low-level width t sbl t kcy4 ns sb0, 1 high-level width t sbh t kcy4 ns *: r l and c l are load resistance and load capacitance of the so output line.
49 m pd75328 ac timing test point (excluding x1 and xt1 inputs) x1 input v dd ?.5v 0.4 v t xl t xh 1/f x xt1 input v dd ?.5v 0.4 v t xtl t xth 1/f xt ti0 t til t tih 1/f ti clock timing ti0 timing test points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd
50 m pd75328 serial transfer timing three-line serial i/o mode: sck t kl1 t kh1 t kcy1 output data t sik1 t ksi1 t kso1 input data si so two-line serial i/o mode: sck t kl2 t kh2 t kcy2 t sik2 t ksi2 t kso2 sb0,1
51 m pd75328 serial transfer timing bus release signal transfer: command signal transfer: sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0,1 t kh3,4 t sbk t ksb interrupt input timing: int0, 1, 2, 4 kr0-7 t intl t inth reset input timing: reset t rsl sck t kl3,4 t kcy3,4 t sik3,4 t ksi3,4 t kso3,4 sb0,1 t kh3,4 t sbk t sbh t sbl t ksb
52 m pd75328 low-voltage data retention characteristics of data memory in stop mode (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply v dddr 2.0 6.0 v voltage data retention supply i dddr v dddr = 2.0 v 0.1 10 m a current* 1 release signal set time t srel 0 m s oscillation stabilization t wait released by reset 2 17 /f x ms wait time* 2 released by interrupt *3 ms *1: does not include current flowing through internal pull-up resistor 2: the oscillation stabilization wait time is the time during which the cpu is stopped to prevent unstable operation when oscillation is started. 3: depends on the setting of the basic interval timer mode register (btm) as follows: btm3 btm2 btm1 btm0 wait time ( ): f xx = 4.19 mhz C0002 20 /f xx (approx. 250 ms) C0112 17 /f xx (approx. 31.3 ms) C1012 15 /f xx (approx. 7.82 ms) C1112 13 /f xx (approx. 1.95 ms) data retention timing (releasing stop mode by reset) data retention timing (standby release signal: releasing stop mode by interrupt) stop mode data retention mode stop instruction execution v dd reset v dddr t srel t wait operation mode internal reset operation halt mode stop mode data retention mode stop instruction execution v dd v dddr t srel t wait operation mode halt mode standby release signal (interrupt request)
53 m pd75328 11. characteristic curves (reference value) 5000 1000 500 (t = 25?c) high-speed mode pcc=0011 middle-speed mode pcc=0010 low-speed mode pcc=0000 main system clock halt mode main system clock stop mode + subsystem clock operation mode i vs v (crystal oscillation: 4.19 mhz) dd dd 100 50 main system clock stop mode + 32 khz oscillation only or subsystem clock halt mode 10 5 2 0123 4567 power supply valtage v [v] dd power supply current i [ a] dd m x1 x2 xt1 xt2 22 pf 22 pf 22 pf 22 pf v dd v dd crystal 4.19 mhz crystal 32.768 khz 330 k w a
54 m pd75328 5000 1000 500 (t = 25?c) high-speed mode pcc=0011 middle-speed mode pcc=0010 low-speed mode pcc=0000 main system clock halt mode main system clock stop mode + subsystem clock operation mode i vs v (ceramic oscillation: 4.19 mhz) dd dd 100 50 main system clock stop mode + 32 khz oscillation only or subsystem clock halt mode 10 5 2 0123 4567 power supply valtage v [v] dd power supply current i [ a] dd m x1 x2 xt1 xt2 30 pf 30 pf 22 pf 22 pf v dd v dd ceramic oscillator csa4.19mg crystal 32.768 khz 330 k w a
55 m pd75328 5000 1000 500 (t = 25?c) high-speed mode pcc=0011 middle-speed mode pcc=0010 low-speed mode pcc=0000 main system clock halt mode main system clock stop mode + subsystem clock operation mode i vs v (ceramic oscillation: 2.00 mhz) dd dd 100 50 main system clock stop mode + 32 khz oscillation only or subsystem clock halt mode 10 5 2 0123 4567 power supply valtage v [v] dd power supply current i [ a] dd m x1 x2 xt1 xt2 30 pf 30 pf 22 pf 22 pf v dd v dd ceramic oscillator csa2.00mg crystal 32.768 khz 330 k w a
56 m pd75328 (v = 5 v, t = 25?c) dd (v = 3 v, t = 25?c) dd 3 2 1 0 12345 f [mhz] x 0 12345 f [mhz] x 0.6 0.5 0.4 0.3 0.2 0.1 i [ma] dd i [ma] dd x1 x2 external clock x1 x2 external clock high-speed mode pcc = 0011 main system clock halt mode middle-speed mode pcc = 0010 low-speed mode pcc = 0000 high-speed mode pcc = 0011 middle-speed mode pcc = 0010 low-speed mode pcc = 0000 main system clock halt mode 40 30 (t = 25?c) i [ma] ol 20 10 0 1234 5 v [v] ol 40 30 i [ma] ol 20 10 0 1234 5 v [v] ol v = 6 v dd v = 5 v dd v = 3 v dd v = 6 v dd v = 4 v dd v = 3 v dd a a a (t = 25?c) a v = 2.7 v dd v = 4 v dd v = 5 v dd v = 2.7 v dd i dd vs f x v ol vs i ol (port 0, 2, 6, 7, 8) v ol vs i ol (port 3, 4, 5) i dd vs f x
57 m pd75328 20 15 10 5 0 12345 v ?v [v] dd oh i [ma] oh 20 15 10 5 0 12345 v ?v [v] dd oh i [ma] oh (t = 25?c) v = 6 v dd v = 5 v dd v = 3 v dd v = 2.7 v dd a (t = 25?c) a v = 4 v dd v = 2.7 v dd v = 3.5 v dd v = 6 v dd v = 5 v dd v = 4 v dd v = 3 v dd v oh vs i oh (p83) v oh vs i oh (except for p83)
58 m pd75328 (v = 5 v, t = 25?c) dd 800 700 600 500 400 300 200 100 0 ?00 ?00 ?00 ?00 ?00 ?00 0 12345 v [v] ol 12345 v ?v [v] dd oh i [ a] m ol i [ a] m oh number of simultaneous output* : 1 2 3 4 number of simultaneous output : 1 2 3 4 250 i [ a] m ol ?00 i [ a] m oh 123 v [v] ol 123 v ?v [v] dd oh number of simultaneous output* : 1 200 150 100 50 0 ?50 ?00 ?0 0 number of simultaneous output : 1 2 3 4 2 3 4 a (v = 5 v, t = 25?c) dd a (v = 3 v, t = 25?c) dd a (v = 3 v, t = 25?c) dd a v ol vs i ol (bp0-3, bp4-7) v oh vs i oh (bp0-3, bp4-7) * of pins bp0-bp3 and bp4-bp7, for each, the number of pins simultaneously outputting the same level. v ol vs i ol (bp0-3, bp4-7) v oh vs i oh (bp0-3, bp4-7)
59 m pd75328 12. package drawings a m f b 60 61 40 k l 80 pin plastic qfp ( 14) 80 1 21 20 41 g d c detail of lead end s q p m i h j 55? n s80gc-65-3b9-3 item millimeters inches a b c d f g h i j k l 17.2 0.4 14.0 0.2 0.8 0.30 0.10 0.13 14.0 0.2 0.677 0.016 0.031 0.031 0.005 0.026 (t.p.) 0.551 note m n 0.10 0.15 1.6 0.2 0.65 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.012 0.551 0.8 0.2 0.031 p 2.7 0.106 0.677 0.016 17.2 0.4 0.8 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008

61 m pd75328 13. recommended soldering conditions it is recommended that m pd75328 be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document "semiconductor devices mounting manual" (iei-616). the soldering methods and conditions are not listed here, consult nec. table 13-1 soldering conditions m pd75328gc - xxx - 3b9: 80-pin plastic qfp ( n n 14 mm) soldering method soldering conditions symbol for recommended condition wave soldering soldering bath temperature: 260 c max., ws60-162-1 time: 10 seconds max., number of times: 1, pre-heating temperature: 120 c max. (package surface temperature), maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125 c). infrared reflow package peak temperature: 230 c, ir30-162-1 time: 30 seconds max. (210 c min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125 c) vps reflow package peak temperature: 215 c, vp15-162-1 time: 40 seconds max. (200 c min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125 c) pin partial heating pin temperature: 300 c max., time: 3 seconds max. (per side) *: number of days after unpacking the dry pack. storage conditions are 25 c and 65%rh max. caution: do not use two or more soldering methods in combination (except the pin partial heating method). a model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235 c, number of times: 2, and an extended number of days) is also available. for details, consult nec. notice h
m pd75328 name m pd75328 m pd75308 item rom (bytes) 8064 ram ( 4 bits) 512 general-purpose ? 4-bit manipulation: 8 4 banks register ? 8-bit manipulation: 4 4 banks instruction cycle selectable from 0.95 m s, 1.91 m s, 15.3 m s (main system clock: operating at 4.19 mhz) and 122 m s (subsystem clock: operating at 32.768 khz) input/ coms 8 (shared with 8 (shared with output input int, si, so) int, si, so) port cmos 20 (4 lines can 16 (4 lines can input/ directly drive directly drive output led) led) cmos 4/8 (shared with segment output, 4/8 (shared with segment output, output can be selected using software) can be selected using software) n-ch 8 (can directly drive led, can be 8 (can directly drive led, can be input/ sustain with 10 v, and can be sustain with 10 v, and can be output pulled up by mask option) pulled up by mask option) timer/counter ? timer/event counter ? basic interval timer ? watch timer serial interface ? built-in nec-standard serial bus interface (sbi) ? normal clock synchronized serial interface is also possible a/d converter 6-channel analog input, 8-bit resolution vector interrupt external: 3, internal: 3 test input external: 1, internal: 1 instruction set ? bit data set/reset/test/boolean operation ? 4-bit data transfer/arithmetic/increment/decrement/comparison ? 8-bit data transfer display function lcd controller lcd controller ? segment outputs: 20 ? segment outputs: 32 (4/8 can be set for output port by using (4/8 can be set for output port by using software) software) ? common outputs: 4 ? common outputs: 4 ? display mode ? display mode (static, 1/2, 1/3, 1/4) (static, 1/2, 1/3, 1/4) ? built-in step-down resistor network for lcd ? built-in step-down resistor network for lcd drive voltage supply (mask option) drive voltage supply (mask option) operating voltage 2.7 to 6.0 v package 80-pin plastic qfp ( 14mm) 80-pin plastic qfp (14 20 mm) appendix a. comparison of features between m pd75328 and m pd75308 36 (44 max.) 32 (40 max.) can be pulled up using software, except for p00 can be pulled up using software, except for p00 62
62 m pd75328 name m pd75328 m pd75308 item rom (bytes) 8064 ram ( 4 bits) 512 general-purpose ? 4-bit manipulation: 8 4 banks register ? 8-bit manipulation: 4 4 banks instruction cycle selectable from 0.95 m s, 1.91 m s, 15.3 m s (main system clock: operating at 4.19 mhz) and 122 m s (subsystem clock: operating at 32.768 khz) input/ coms 8 (shared with 8 (shared with output input int, si, so) int, si, so) port cmos 20 (4 lines can 16 (4 lines can input/ directly drive directly drive output led) led) cmos 4/8 (shared with segment output, 4/8 (shared with segment output, output can be selected using software) can be selected using software) n-ch 8 (can directly drive led, can be 8 (can directly drive led, can be input/ sustain with 10 v, and can be sustain with 10 v, and can be output pulled up by mask option) pulled up by mask option) timer/counter ? timer/event counter ? basic interval timer ? watch timer serial interface ? built-in nec-standard serial bus interface (sbi) ? normal clock synchronized serial interface is also possible a/d converter 6-channel analog input, 8-bit resolution vector interrupt external: 3, internal: 3 test input external: 1, internal: 1 instruction set ? bit data set/reset/test/boolean operation ? 4-bit data transfer/arithmetic/increment/decrement/comparison ? 8-bit data transfer display function lcd controller lcd controller ? segment outputs: 20 ? segment outputs: 32 (4/8 can be set for output port by using (4/8 can be set for output port by using software) software) ? common outputs: 4 ? common outputs: 4 ? display mode ? display mode (static, 1/2, 1/3, 1/4) (static, 1/2, 1/3, 1/4) ? built-in step-down resistor network for lcd ? built-in step-down resistor network for lcd drive voltage supply (mask option) drive voltage supply (mask option) operating voltage 2.7 to 6.0 v package 80-pin plastic qfp ( 63 m pd75328 ev-9200gc-80 appendix b. development tools the following development support tools are readily available to support development of systems using m pd75328: prom writing tools hardware ie-75000-r * 1 in-circuit emulator for 75x series ie-75001-r ie-75000-r-em * 2 emulation board for ie-75000-r and ie-75001-r ep-75328gc-r emulation prove for m pd75328gc, provided with 80-pin conversion socket ev-9200gc-80. pg-1500 prom programmer pa-75p328gc prom programmer adapter solely used for m pd75p328gc. it is connected to pg-1500. software ie control program pg-1500 controller ra75x relocatable assembler *1: maintenance product 2: not provided with ie-75001-r. 3: ver.5.00/5.00a has a task swap function, but this function cannot be used with this software. remarks: for development tools from other companies, refer to 75x series selection guide (if-151). host machine ? pc-9800 series (ms-dos tm ver.3.30 to ver.5.00a* 3 ) ? ibm pc/at tm (pc dos tm ver.3.1) h
m pd75328 64 appendix c. related documents h
m pd75328 65 1 static electricity (all mos devices) exercise care so that mos devices are not adversely influenced by static electricity while being handled. the insulation of the gates of the mos device may be destroyed by a strong static charge. therefore, when transporting or storing the mos device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case nec uses for packaging and shipment, and use grounding when assembling the mos device system. do not leave the mos device on a plastic plate and do not touch the pins of the device. handle boards on which mos devices are mounted similarly . 2 processing of unused pins (cmos devices only) fix the input level of cmos devices. unlike bipolar or nmos devices, if a cmos device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. therefore, fix the input level of the device by using a pull-down or pull-up resistor. if there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to v dd or gnd through a resistor. refer to processing of unused pins in the documents of each devices. 3 status before initialization (all mos devices) the initial status of mos devices is undefined upon power application. since the characteristics of an mos device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. the output status of pins, i/o setting, and register contents upon power application are not guaranteed. however, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. when using a device with a reset function, be sure to reset the device after power application. general notes on cmos devices
m pd75328 66 [memo] no p art of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for the applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime system, etc. ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation. m4 92.6

▲Up To Search▲

Price & Availability of UPD75328

	To Download UPD75328 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .